Currently, Cognovo offers two MCE products: MCE 120 and MCE 160. Details on each are available in the related links section of this page below.
The Data Plane consists of a number of Ardbeg Vector Signal Processors (VSP) programmed in high level C code. The scalable multi-processor VSP Sub-system is able to execute the entire signal processing requirements of the modem from front-end symbol processing, right through to back-end bit level processing.
The VSP combines an advanced Very Long Instruction Word (VLIW) architecture with a power efficient vector datapath designed to fully exploit the instruction and data level parallelism inherent in wireless algorithms. The unique capabilities of the VSP mean that even complex MIMO OFDM equalisation can be developed in software and executed in realtime at a power consumption which is comparable with the dedicated hardware which it replaces.
The VSP sub-system is supported by a high speed bus which includes an RF IC interface unit and a programmable Forward Error Correction (FEC) engine for Turbo / LDPC.
The Control Plane manages and sequences the operation of the Data Plane ensuring that data movement and the processing of that data are coordinated according to the on-air requirements of the various RAT specifications. The subsystem is built around a standard ARM processor and related support components to ensure ease of use and an efficient power-performance trade off.
The dedicated sub-frame Sequence Processor provides a deterministic and power-efficient means of controlling and scheduling individual PHY tasks running on the VSP, especially in low power states such as idle mode and sleep mode. The Sequencer executes Layer 1 PHY procedures and keeps track of on-air timing requirements. It is also able to respond to interrupts within the MCE with low latency. In this way the same real-time determinicity and reliability of a dedicated hardware approach is retained even whilst the modem is now implemented in software.