Both SDKs are designed to integrate within a traditional modem development flow and can be used in conjunction with existing tools such as Matlab, Co-ware or SPW.
Re-verification with existing reference simulations is supported to ensure system integrity is maintained throughout the development process.
More detail on Design Flow can be found here.
VSP Kernel SDK
The Kernel SDK enables developers to create, debug, profile and optimise Physical Layer algorithm kernels, such as FFTs, or FIRs which are linked together to create larger functions within the Modem, such as Downlink or Uplink. This is the point of entry for existing developments, since standard fixed-point C code implementations of key algorithms can be readily imported into the toolset and targeted towards the VSP architecture to make a rapid assessment of performance and efficiency prior to using the optimisation tools to reach the best possible results.
Reference kernel libraries are also available to support modem development by providing optimised examples of often used algorithms.The Kernel SDK consists of the following major tools, each available through a command line interface and also fully integrated within the Eclipse IDE:
- Parallelising C Compiler
- Cycle accurate Instruction Set Simulator (ISS)
- Static and dynamic VSP Code Profiler
- VSP Debugger
|Algorithm Design||VSP Code Development||Code Profiling|
SDM System SDK
The System SDK allows PHY kernels to be linked together into system-level PHY procedures, such as DL PDCCH, or Inter-RAT measurement. The System Design Tool allows developers to layout and optimise the overall operation of the Physical Layer in terms of scheduling and data flow, whilst the System Debug and Real-time visualisation tools provide multi-threaded system debug and on-target real time debug / visualisation. The Programmers View MCE System Model allows initial Layer 1 development and integration to be carried out on a PC platform prior to targeting real hardware.The System SDK consists of the following major tools, each available through a command line interface and a GUI:
- System Design Tool - UML based PHY layout, integration and constraint analysis.
- PV System Model - Programmer's View model of MCE for software integration and validation
- System Debug - Multi-core debug supporting VSP and ARM CPU cores.
- Trace Visualisation Tool - Graphical logging and visualisation of real-time modem operation.
|SDT UML PHY Layout||PVModel of MCE||Real-time Event Trace View|