SDM Development Cycle

During the IMPLEMENT phase simultaneous bottom-up (PHY kernel) and top-down (System level) development becomes possible. Because both aspects of modem development can proceed in parallel it is now possible to carry out system level trade-off analyses based on what-if trials at the PHY kernel level. For example, the impact of various levels of equaliser performance may be reviewed at the system level in terms of system timing, memory and power.

During the INTEGRATE phase the Programmers View (PV) model allows Layer 1, PHY and protocol stack integration to be carried out - in software - in a virtual environment. Once integrated, the modem can be verified against reference testbenches and key design criteria, such as timing and memory budgets.

Finally, during the VALIDATE phase the modem is downloaded to target hardware for the purpose of RF integration, validation with test peers and initial field trials. Cognovo provide the SDM Development Platform which uses a high performance SDM baseband IC as a fast-track vehicle to support this phase.

A key benefit of SDM is that the modem is now fully validated even before the target silicon is available. The only silicon dimensioning information required (processing performance, memory and power consumption) is available during the initial implementation phase. This means that both the modem development and silicon development may be fully in parallel.

Furthermore, at all points of this process the same real-time log, trace and debug tools are used to verify correct operation.